The present disclosure relates generally to the field of fabrication of semiconductor devices, and more specifically to a method of fabricating a fin type field effect transistor (FinFET) or portion thereof.
Double-gate MOSFETs are MOSFETs that incorporate two gates into a single device. These devices are also known as FinFETs due to their structure including a thin “fin” extending from a substrate. Silicon based FinFETs have been successfully fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a substrate with an overlying insulating layer with a thin ‘fin’ extending from the substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. The double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
Germanium FinFET (Ge-FinFET) fabrication has provided numerous difficulties however. Ge-FinFET devices include a fin formed at least in part, of germanium (as opposed to silicon fin). Typical Ge-FinFET fabrication includes patterning a germanium layer on a germanium-on-insulator (GOI) substrate to form a narrow Ge-fin. However, GOI substrates are not widely used in production processes. Furthermore, GOI substrates may provide issues with crystalline quality particularly at larger wafer sizes, for example, 300 mm wafers. Further still, the GOI etch process will require extensive development in order to make it suitable for production fabrication processes. In contrast, silicon based FinFET processes have been well developed.
As such, an improved Ge-FinFET device and fabrication method of a FinFET element is desired.